1. Field of the Invention
The present invention relates to a semiconductor device having a multi-layered interconnection structure in which interconnections are formed in a plurality of layers over the main surface of a semiconductor substrate, and particularly to an improvement for reducing the noise superimposed on the signals transmitted through the interconnections or cross-talk.
2. Description of the Background Art
Semiconductor integrated circuits represented by the LSIs (Large Scale Integrated circuits) have a large number of semiconductor elements formed in active regions in the main surface of semiconductor substrates. These semiconductor devices are electrically isolated from each other by element isolation structure such as STI (Shallow Trench Isolation). The semiconductor elements are selectively connected through electric conductors (interconnections) to realize the function of an integrated circuit.
Usually, polysilicon which contains a dopant at a high concentration or metal is used as the material of the electric conductor. Used as the metal interconnections are aluminum, copper, tungsten, molybdenum, etc. The gate structure, which is an interconnection formed in close proximity to the main surface of the semiconductor substrate, is formed by using aluminum, polysilicon, polysilicon/metal silicide double-layer structure, tungsten, molybdenum, etc. Metals such as tungsten, cobalt, nickel, titanium, zirconium, platinum, etc. are used for the metal silicide.
Two methods have conventionally been suggested as methods for forming the interconnections. In a first method, an interconnection material is deposited over the entire main surface of a semiconductor substrate by CVD (Chemical Vapor Deposition), sputtering, etc. and then a resist is applied. Then it is patterned through a transfer process to form a resist mask. The interconnection material is then anisotropically etched by using the resist mask to form an interconnection pattern. This first method is referred to as “etching method” in this specification.
In a second method, a resist is applied on an insulating film formed on the main surface of a semiconductor substrate and the resist is patterned through a transfer process to form a resist mask. Then an anisotropic etching is performed by using this resist mask to selectively form trenches in the insulating film. Next the trenches are filled with an interconnection material by using CVD or deposition. Subsequently, the surface is smoothed out by CMP (Chemical Mechanical Polishing) so that the surface of the insulating film and the surface of the interconnection material approximately coincide with each other. This second method is referred to as damascene method.
First, an interconnection formation process by the etching method will be described. FIGS. 27 to 29 are manufacture process diagrams showing a conventional interconnection formation process by the etching method.
The process shown in FIG. 27 is performed first. In the process of FIG. 27, first, STIs 102 as the element isolation structure and MOSFETs as semiconductor elements are formed on the main surface of the semiconductor substrate 101 which is a silicon substrate. Each MOSFET has a pair of N+ source/drain regions (a set of a source region and a drain region is referred to as “source/drain regions” together) 106, a pair of N− source/drain regions 105 and a channel region 104, which are regions selectively formed in the main surface of the semiconductor substrate 101. A gate electrode having a double-layer structure of a doped polysilicon layer 108 and a tungsten silicide layer 109 is selectively formed on the main surface, which faces to the channel region 104 through a gate insulating film 107. Further, the gate electrode is covered by sidewalls 111 with a silicon oxynitride film 110 interposed therebetween.
The STIs 102 are selectively formed in the main surface of the semiconductor substrate 101 to electrically separate adjacent MOSFETs. A channel stopper layer 103 is formed in the semiconductor substrate 101 prior to the formation of the MOSFETs.
After the formation of the MOSFETs and STIs 102, an interlayer insulating film 112 is deposited over the main surface of the semiconductor substrate 101 so thick as to cover the sidewalls 111. Next, through holes 113 are selectively formed in the interlayer insulating film 112 right above the N+ source/drain regions 106, and aluminum 114 is deposited to fill the through holes 113 and to cover the interlayer insulating film 112. The aluminum plugs buried in the through holes 113 function as the source/drain electrodes of the MOSFETs.
The aluminum 114 may precipitate on the semiconductor substrate 101 to cause leakage, since the semiconductor substrate 101 is exposed in the bottoms of the through holes 113. To prevent this, a barrier metal layer (not shown) is deposited on the bottoms and sides of the through holes 113. TiN (titanium nitride) is used as the material of the barrier metal layer, for example.
Next, an ARC film (Anti Reflection Coating) 115 is deposited on the aluminum 114. The ARC film 115 is deposited to prevent so-called halation in which exposure light used in a transfer process is reflected at the surface of the aluminum 114 to cause the resist pattern to be formed thinner than the designed form. Subsequently, a resist is applied on the ARC film 115 and a resist mask 116 is formed through a transfer process.
Next, the process shown in FIG. 28 is performed. In the process of FIG. 28, first, an anisotropic etching is applied to the aluminum 114 by using the resist mask 116 to form aluminum interconnections 150. An interlayer insulating film 117 is then deposited. At this time, along the main surface of the semiconductor substrate 101, while a small step height 120 appears on the surface of the interlayer insulating film 117 in the area 118 where the density of the aluminum interconnections 150, or the interconnection density, is high, a large step height 121 appears in the area 119 where the interconnection density is low. Such a large difference in level like the step height 121 causes problems in the later processes; this degrades the accuracy of patterning by transfer in the process of depositing aluminum on the interlayer insulating film 117 and forming a second aluminum interconnection through a transfer process, for example.
In order to avoid this problem, the interlayer insulating film 117 may be smoothed by CMP prior to the deposition of aluminum on the interlayer insulating film 117. However, due to the uneven interconnection density, the CMP process cannot sufficiently smooth the nonuniform topography on the surface of the interlayer insulating film 117.
A method for avoiding this problem is known, where, as shown in FIG. 29, dummy aluminum interconnections 122 which do not contribute to the operation of the MOSFETs are formed to fill the intervals between the less densely arranged aluminum interconnections 150 so as to compensate for the unevenness of the interconnection density. This method avoids the formation of areas with less densely arranged interconnections and reduces the step height 123 appearing on the surface of the interlayer insulating film 117, thus enhancing the flatness of the surface of the interlayer insulating film 117 after CMP. In this way, the formation of the dummy interconnection pattern is considered to be essential to obtain improved flatness on the surface of the structure formed after CMP above the semiconductor substrate 101.
Next, an interconnection formation process by the damascene method will be described. A technique for enhancing the operating speed of LSIs is known, where copper (Cu), which has lower interconnection resistance than aluminum (Al), is used as the interconnection material in the LSIs. For example, at 20° C., Cu has a resistivity of as low as 1.70 μΩ·cm while that of Al is 2.74 μΩ·cm. However, since it is difficult to form copper interconnections by the above-described etching method, the damascene method is widely adopted in the process of forming copper interconnections.
FIGS. 30 to 36 are manufacture process diagrams showing a conventional interconnection formation process by the damascene method. First, as shown in FIG. 30, STIs 102 as element isolation structure and MOSFETs as semiconductor elements are formed on the main surface of the semiconductor substrate 101 which is a silicon substrate. As to the structure of the MOSFETs, the MOSFETs shown in FIG. 30 have the same structure as the MOSFETs shown in FIG. 27 except that they each have a silicide layer 145 on the N+ source/drain regions 106.
After the formation of the MOSFETs and STIs 102, an interlayer insulating film 127 is deposited over the main surface of the semiconductor substrate 101 so thick as to cover the sidewalls 111. Next, through holes 124 are selectively formed in the interlayer insulating film 127 right above the N+ source/drain regions 106. In this stage of process, the interconnection trenches 125 shown in FIG. 30 are not formed yet. An insulating film having a relative dielectric constant of about two to three is used as the interlayer insulating film 127, for example. While a silicon oxide film has a relative dielectric constant of about 3.9, an insulating film having a lower relative dielectric constant is used to reduce the parasitic capacitance between adjacent gate electrodes or between the gate electrodes and plugs buried in the through holes 124 so as to enhance the operating speed of the semiconductor device.
Next, resist plugs (not shown) are deposited to fill the through holes 124. Subsequently a resist mask is formed and anisotropic etching is applied to the interlayer insulating film 127 to form interconnection trenches 125. This process may form an area 129 in which the interconnection trenches 125 are formed densely and an area 130 in which they are formed less densely.
Subsequently, the resist plugs filling the through holes 124 are removed and a barrier metal 126 is deposited to cover the bottoms and sides of the through holes 124, the bottoms and sides of the interconnection trenches 125, and the upper surface of the interlayer insulating film 127. A film of metal nitride such as WN, TiN, TaN etc. is used as the material of the barrier metal 126. The barrier metal 126 is formed to prevent the metal atoms in the through holes 124 and the interconnection trenches 125 from thermally diffusing into the interlayer insulating film 127.
In the next process shown in FIG. 31, copper is deposited by CVD, PVD (Physical Vapor Deposition) etc. to fill the through holes 124 and the interconnection trenches 125 and to cover the top surface of the interlayer insulating film 127. At this time, while a small step height 132 may appear on the surface of the deposited copper in the high interconnection density area 129, a large step height 133 may appear in the low interconnection density area 130. When the step heights are nonuniform in this way, it is difficult to obtain a sufficiently flat surface even after planarization in the later CMP process.
A method for avoiding this problem is known, where, as shown in FIG. 32, dummy interconnection trenches 134 are formed in the low interconnection density area 130, or large interconnection interval area, to reduce the unevenness of the interconnection intervals. This reduces the irregularities appearing on the surface of the deposited copper so that the topography becomes uniform in the area 129 and area 130.
When copper is deposited by using electroplating apparatus, the nonuniform step heights 132 and 133 on the copper surface as shown in FIG. 31 can be reduced fairly well. However, the nonuniform interconnection density still causes the copper interconnections to be over-polished in the lower interconnection density area 130 in the CMP process. This phenomenon is called “dishing” because observation of the section of an over-polished copper interconnection shows that the top surface of the copper is dented just like the bottom of a dish.
As the interconnection density becomes higher, a larger amount of copper must be removed per unit area, which reduces the polishing rate. Accordingly, the polishing rate is larger in the low interconnection density area 130 than in the high density area 129. Hence, when priority is given to the flatness of the high density area 129, then the copper interconnections in the low density area 130 will be over-polished to cause the dishing. When dishing occurs in a copper interconnection, the cross-sectional area of the copper interconnection is reduced to increase the interconnection delay. That is to say, the operating speed of the semiconductor device is lowered. Avoiding the dishing problem, too, requires the formation of dummy interconnections to make the interconnection density more uniform. This enhances the flatness of the copper interconnections at the same time.
In the next process step shown in FIG. 33, first, CMP is applied to smooth the top surface of copper using the interlayer insulating film 127 as the stopper. This CMP process smoothes the surface so that the top surface of the interlayer insulating film 127 and the top surface of the copper interconnections approximately coincide with each other. In this process, the barrier metal 126 formed on the upper surface of the interlayer insulating film 127 is also removed. The interconnections 125b and the dummy interconnections 134b are formed in this process step. FIG. 33 shows the two kinds of interconnections with different types of hatching so that they can be clearly distinguished, though both are made of the same material, copper.
Next, interlayer insulating films 135 and 136 are deposited. For the material of the interlayer insulating film 135, silicon nitride or silicon oxynitride is used, for example. The interlayer insulating film 135 is formed for the purpose of preventing oxidation of the exposed surface of the copper interconnections. Silicon nitride and silicon oxynitride have the property of preventing oxidizing agent (oxygen, water, etc.) in the air or in the gas atmosphere used in semiconductor device manufacturing apparatus from thermally diffusing or drifting to reach the copper interconnections. For the material of the interlayer insulating film 136, an insulator having a relative dielectric constant of about two to three is used, for example. An insulator having a relatively small relative dielectric constant is used for the interlayer insulating film 136 to reduce the capacitance between interconnections so as to shorten the delay time during the operation of the semiconductor device.
Next, anisotropic etching is applied by using a resist mask (not shown) patterned through a transfer process to form through holes 137 in the interlayer insulating films 135 and 136. Then organic plugs 138 are formed to fill the lower half of the through holes 137.
In the next process shown in FIG. 34, first, a resist (not shown) is deposited and patterned through a transfer process to form a resist mask (not shown). Next, anisotropic etching is applied by using the resist mask to form interconnection trenches 139 and dummy interconnection trenches 140 in the interlayer insulating film 136. Like the dummy interconnection trenches 134 formed in the interlayer insulating film 112, the dummy interconnection trenches 140 are formed so that flatter copper interconnections can be obtained in the following CMP process.
In the next process shown in FIG. 35, first, a barrier metal 141 is deposited and then copper 142 is deposited to fill the through holes 137 and interconnection trenches 139 and 140 and also to cover the top surface of the interlayer insulating film 136. The step height 143 is formed low because of the dummy interconnection trenches 140.
In the next process shown in FIG. 36, first, CMP is applied to smooth the top surface of copper by using the interlayer insulating film 136 as a stopper. The presence of the dummy interconnection trenches 140 enables improved flatness. This process step forms copper plugs in the through holes 137, copper interconnections 144 in the interconnection trenches 139, and dummy copper interconnections 145 in the dummy interconnection trenches 140.
Next, for example, silicon nitride is deposited to form an interlayer insulating film 146 and SiOF is deposited to form an interconnection insulating film 147.
These series of process steps of forming interconnection trenches and through holes in an interlayer insulating film, forming a barrier metal, burying and depositing copper, and applying CMP to remove excess copper, is called “dual damascene method.” The dummy patterns are formed not only to improve the flatness in the CMP process but also to correct the proximity effect in which the finished resist form is affected by the proximate pattern form in the transfer process.
As described above, the dummy interconnections 122 of FIG. 29 and the dummy interconnections 134b and 145 of FIG. 36 are formed to improve the flatness of the interconnections and interlayer insulating films, and they are not involved directly in the circuit function of the integrated circuitry formed in the semiconductor device. Accordingly, in conventional applications, the dummy interconnections are left in an electrically floating state without being connected to any circuit terminals in the semiconductor device.
The recent progress toward highly integrated LSIs has narrowed the interconnection pitch and increased the operating frequency to hundreds of megahertz to several gigahertz, and as a result some problems are being encountered due to the dummy interconnections left in an electrically floating state. First, in an interconnection, e.g. in a precharge interconnection, the potential varies from 0 V (ground potential) to VDD (higher power-supply potential) in a short time and then the passage of current creates a magnetic field loop around that interconnection. This magnetic field loop causes a displacement current in an adjacent dummy interconnection through electromagnetic induction. The displacement current flows until the dummy interconnection potential becomes uniform. Since the dummy interconnection is electrically floating, its potential is determined by the history of the circuit operation. If this displacement current is large, then a magnetic field loop is produced around the dummy interconnection, which induces a displacement current due to electromagnetic induction in another interconnection adjacent to the dummy interconnection. This current is superimposed on the signal as noise.
Second, as a certain interconnection and a dummy interconnection are spaced at a smaller interval, the coupling capacitance becomes larger between them. Accordingly, the amount of image charge occurring on the dummy interconnection increases in accordance with the amount of charge flowing in the interconnection. This image charge affects signal on another interconnection and causes noise.
These two phenomena can be considered to be cross-talk between interconnections through dummy interconnections. Noise of this kind exerts serious effects especially in analog circuitry, which has been a considerable problem.
Japanese Patent Application Laid-Open No.8-222632(1996) (which is referred to as a first reference), Japanese Patent Application Laid-Open No.10-199882(1998) (a second reference), and Japanese Patent Application Laid-Open No.4-179126(1992) (a third reference) are known as reference materials which disclose techniques related to this invention.